As microprocessor systems increase in size and speed, there is need for larger and faster memory arrays. These high-speed memory arrays may contain a large number of memory cells. However, as the number of memory elements increases, the time needed to read and/or write to the individual memory cells may also increase. This may be due to the fact that as the number of memory elements increases in an individual array, the length of the wordline between the supply voltage and the individual memory cells may also increase. The increased length of the wordline may directly relate to an increase in the resistance of the wordline. Therefore, as the size of the memory array increases so may the required voltage needed to read the individual memory cells. Additionally, in large memory arrays, the capacitance of the wordline may require an increase in the time required charge to the desired level in order to access a given memory cell. The increase in the time required to charge the may lead to a large cycle time, which may directly limit the access time for the memory. Additionally, the increase in the time required to charge the capacitance may also limit the length of the wordline. As the length of the wordline increases so does the resistance value of the wordline wire. Therefore, the time required to charge the capacitance may be limited by the large RC value associated with a longer wire.
One solution to solve this problem and increase the speed of the memory access time was to break the large single array into a stacked array, which consists of a number of smaller arrays connected in parallel. Although using a stacked memory array may increase access time of the memory cells, there may be several drawbacks associated with using multiple arrays. First, using stacked memory arrays may increase the overall cost of the system. The amount of silicon required to produce a stacked array increases proportionally to the number of memory arrays contained in the stack. Therefore as the number of memory arrays increases, so does the manufacturing costs. In addition, each array in the memory stack may require its own supporting circuitry. Increasing the amount of supporting circuit may also contribute to increasing the manufacturing cost. Next, the stacked memory arrays may increase the load on the system. For example, each individual memory array in the memory stack may be attached to the external bus, which in turn may increase the capacitance load on the external bus. Furthermore, the overall power consumption of the system may be increased due to the increased number of memory arrays.